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HT82V36
16-Bit CCD/CIS Analog Signal Processor
Features
* Operating voltage: 3.3V * Low power consumption at 56mW * Power-down mode: Under 1mA * 200mV programmable offset * Input clamp circuitry * Internal voltage reference * Multiplexed byte-wide output (8+8 format) * Programmable 3-wire serial interface * 3.3V digital I/O compatibility * 28-pin SSOP (209mil) package
(clock timing keep low)
* 16-bit 6 MSPS A/D converter * Guaranteed no missing codes * Supports CDS/SHA mode * 1~6 programmable gain
Applications
Low power flatbed document scanners
General Description
The HT82V36 is a complete analog signal processor for CCD imaging applications. It features a 1-channel architecture designed to sample and condition the outputs of linear CCD arrays. It consists of an input clamp, Correlated Double Sampler (CDS), offset DAC and Programmable Gain Amplifier (PGA), and a low power 16-bit A/D converter. The CDS amplifiers may be disabled for use with sensors such as Contact Image Sensors (CIS) and CMOS active pixel sensors, which do not require CDS. The 16-bit digital output is multiplexed into an 8-bit output word that is accessed using two read cycles. The internal registers are programmed through a 3-wire serial interface, which provides gain, offset and operating mode adjustments.
Block Diagram
BANDGAP 1 6 B its A /D C o n v e rte r 16
G IN
CDS
+ 9 B its DAC 9
PGA
MUX
D0~D7
CLAM P
6 R E G IS T E R S
SLO AD SDATA SC LK
Rev. 1.30
1
June 29, 2004
HT82V36
Pin Assignment
CDSCLK1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CDSCLK2 AD CCLK OE DRVDD DRVSS D 7 (M S B ) D6 D5 D4 D3 D2 D1 D 0 (L S B ) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS NC OFFSET V IN G CML NC REFT REFB AVSS AVDD SLO AD SC LK SDATA
H T82V36 2 8 S S O P -A
Pin Description
Pin No. 1 2 3 4 5 6 7~14 15 16 17 18, 27 19, 28 20 21 23 24 25 22, 26 Pin Name CDSCLK1 CDSCLK2 ADCCLK OE DRVDD DRVSS D7~D0 SDATA SCLK SLOAD AVSS AVDD REFB REFT CML VING OFFSET NC I/O DI DI DI DI P P DO DI/DO DI DI P P AO AO AO AI AO 3/4 Description CDS reference clock pulse input CDS data clock pulse input A/D sample clock input Output enable, active low Digital driver power Digital driver ground Digital data output Serial data input/output Clock input for serial interface Serial interface load pulse Analog ground Analog supply Reference decoupling Reference decoupling Internal reference output Analog input Clamp bias level decoupling No connection
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+3.6V Input Voltage .............................VSS-0.3V to VDD+0.3V Storage Temperature ...........................-50C to 125C Operating Temperature ..........................-25C to 75C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.30
2
June 29, 2004
HT82V36
D.C. Characteristics
Symbol Logic Inputs VIH VIL IIH IIL CIN VOH VOL IOH IOL High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance High Level Output Voltage Low Level Output Voltage High Level Output Voltage Low Level Output Voltage 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0.8VDD 3/4 3/4 3/4 3/4 VDD-0.5 3/4 3/4 3/4 3/4 3/4 10 10 10 3/4 3/4 1 1 3/4 0.2VDD 3/4 3/4 3/4 3/4 0.5 3/4 3/4 V V mA mA pF V V mA mA Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit
Logic Outputs
A.C. Characteristics
Symbol Parameter Test Conditions VDD 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Conditions 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Min. Typ. Max. Unit
Maximum Conversion Rate tMAX CDS/SHA Mode ADC Resolution Integral Nonlinear (INL) Differential Nonlinear (DNL) Offset Error Gain Error Analog Inputs RFS Vi Ci Ii Amplifiers PGA Gain at Minimum PGA Gain at Maximum PGA Gain Resolution Programmable Offset at Minimum Programmable Offset at Maximum Offset Resolution Temperature Range tA VADD VDRDD Ptot Operating AVDD DRVDD Total Power Consumption 0 3 3 3/4 3/4 3.3 3.3 56 70 3.6 3.6 3/4 C V V mW Power Supplies 3/4 3/4 3/4 3/4 3/4 3/4 1 5.85 6 -200 200 9 3/4 3/4 3/4 3/4 3/4 3/4 V/V V/V Bits mV mV Bits Full-scale Input Range Input Limits Input Capacitance Input Current 1.3 AVDD-0.3 3/4 3/4 1.4 3/4 TBD TBD 1.6 AVDD+0.3 3/4 3/4 Vp-p V pF mA 6 3/4 3/4 -1 -100 3/4 3/4 16 16 3/4 TBD TBD 3/4 3/4 3/4 2 100 3/4 LSB LSB mV %FSR MHz Accuracy (Entire Signal Path)
Power Consumption
Rev. 1.30
3
June 29, 2004
HT82V36
Timing Specification Symbol Clock Parameters tADCLK tADH tADL tC1 tC2 tC3 tC2ADF tADFC1 tADFC2 tAD Pixel Rate Clock ADCCLK Pulse High Width ADCCLK Pulse Low Width CDSCLK1 Pulse Width CDS Mode CDSCLK2 Pulse Width SHA Mode CDSCLK2 Pulse Width CDSCLK2 Falling to ADCCLK Falling ADCCLK Falling to CDSCLK1 Rising ADCCLK Falling to CDSCLK2 Rising Analog Sampling Delay 166 80 80 20 20 40 60 2 2 5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 ns ns ns ns ns ns ns ns ns ns Parameter Min. Typ. Max. Unit
Serial Interface fSCLK tLS tLH tDS tDH tRDV Data Output tOD Output Delay Latency (Pipeline Delay) 3/4 3/4 8 9 3/4 3/4 ns Cycles Maximum SCLK Frequency SLOAD to SCLK Setup Time SCLK to SLOAD Hold Time SDATA to SCLK Rising Setup Time SCLK Rising to SDATA Hold Time Falling to SDATA Valid 10 10 10 10 10 10 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 MHz ns ns ns ns ns
Functional Description
Integral Nonlinear (INL) Integral nonlinear error refers to the deviation of each individual code from a line drawn from zero scale through positive full scale. The point used as zero scale occurs 1 /2 LSB before the first code transition. Positive full scale is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinear (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 16-bit resolution indicates that all 4096 codes, respectively, must be present over all operating ranges. Offset Error The first ADC code transition should occur at a level 1/2 LSB above the nominal zero scale voltage. The offset error is the deviation of the actual first code transition level from the ideal level. Gain Error The last code transition should occur for an analog value 1/2 LSB below the nominal full-scale voltage. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions. Aperture Delay The aperture delay is the time delay that occurs when a sampling edge is applied to the HT82V36 until the actual sample of the input signal is held. Both CDSCLK1 and CDSCLK2 sample the input signal during the transition from high to low, so the aperture delay is measured from each clocks falling edge to the instant the actual internal sample is taken.
Rev. 1.30
4
June 29, 2004
HT82V36
Internal Register Descriptions Register Name Configuration Reserved Reserved PGA Reserved Reserved Offset Reserved Address A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Internal Register Map D8 D7 D6 D5 D4 D3 D2 D1 Output delay 1=On D0 1 byte out (High-byte only) 1=On 0=Off* MSB LSB X 0 0 MSB LSB D8 0 D7 0 D6 1 D5 1 Data Bits D4 CDS on D3 D2 D1 D0
Enable Output 1byte Clamp Power Delay out Voltage Down
CDS operation Clamp bias Power-down Set to 0 Set to 0 Set to 1 Set to 1 1=CDS mode* 1=2.5V* 0=SHA mode 0=2V 1=On
0=Off (Normal)* 0=Off*
Configuration Register Settings Note: * Power-on default value PGA Gain Register Bits D7 and D6 in the register must be set low, and bits D5 through D0 control the gain range in 64 increments. See figure for a graph of the PGA gain versus PGA register code. The coding for the PGA register is straight binary, with an all zero words corresponding to the minimum gain setting (1x) and an all one word corresponding to the maximum gain setting (5.85x). The PGA has a gain range from 1x (0dB) to 5.85x (15.3dB), adjustable in 64 steps. The Figure shows the PGA gain as a function of the PGA register code. Although the gain curve is approximately linear in dB, the gain in V/V varies in non5.85 linear proportion with the register code, according to the following the equation: Gain= 63 - G 1+ 4.85 ( ) 63 Where G is the decimal value of the gain register contents, and varies from 0 to 63.
15 12 ) 9 G A IN -d B ( 6 3 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 6063 P G A r e g is te r v a lu e - - D e c im a l 5 .8 5 5 .0 4 .0 3 .0 2 .0 1 .0 G A IN -V /V ( )
PGA Gain Transfer Function
Rev. 1.30
5
June 29, 2004
HT82V36
D8 Set to 0 0 0 D7 Set to 0 0 0 D6 Set to 0 0 0 D5 MSB 0 0 0 0 0 0 . . . 1 1 0 0 0 0 D4 D3 D2 D1 D0 LSB 0* 1 1.0 1.013 . . . 5.43 5.85 0.0 0.12 . . . 14.7 15.3 Gain (V/V) Gain (dB)
0 0
0 0
0 0
1 1
1 1
1 1
1 1
0 1
PGA Gain Register Settings Note: * Power-on default value Offset Register Bits D8 through D0 control the offset range from -200mV to 200mV in 512 increments. The coding for the offset registers is sign magnitude, with D8 as the sign bit. The Table shows the offset range as a function of the bits D8 through D0. D8 MSB 0 0 0 0 0 0 0 0 0 0 0 0 . . . 1 0 0 . . . 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 LSB 0* 1 0 0.78 . . . 200 0 -0.78 . . . -200 Offset (mV)
0 1 1
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 1
1
1
1
1
1
1
1
1
Note: * Power-on default value
Timing Diagrams
SDATA SC LK tL
S
R /W b
tD
H
A2
A1
A0
tD
S
D8
D7
D6
D5
D4
D3
D2
D1
D0
tL
H
SLO AD
Serial Write Operation Timing
SDATA SC LK
R /W b
A2
A1
A0
D8
tR
D7
DV
D6
D5
D4
D3
D2
D1
D0
tL
S
tL
H
SLO AD
Serial Read Operation Timing
Rev. 1.30
6
June 29, 2004
HT82V36
P ix e l (N + 3 ) A n a lo g In p u t tA
D
P ix e l (N + 4 )
P ix e l (N + 5 )
P ix e l (N + 6 )
P ix e l (N + 7 )
P ix e l (N + 8 )
P ix e l (N + 9 )
P ix e l (N + 1 0 )
tC
1
CDSCLK1 tC
2
CDSCLK2 tA
D CLK
tA AD CCLK
FC1
tC
2ADF
tA
DL
tA
DH
tO
D
O u tp u t D a ta D7~D0
P ix e l (N -7 )
P ix e l (N -6 )
P ix e l (N -6 )
P ix e l (N -5 )
P ix e l (N -5 )
P ix e l (N -4 )
P ix e l (N -4 )
P ix e l (N -3 )
P ix e l (N -3 )
P ix e l (N -2 )
P ix e l (N -2 )
P ix e l (N -1 )
P ix e l (N -1 )
P ix e l (N )
P ix e l (N )
P ix e l (N + 1 )
P ix e l (N + 1 )
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
1-Channel CDS Mode Timing
P ix e l (N + 4 ) A n a lo g In p u t tA
D
P ix e l (N + 5 )
P ix e l (N + 6 )
P ix e l (N + 7 ) tC
3
P ix e l (N + 8 )
P ix e l (N + 9 )
P ix e l (N + 1 0 )
P ix e l (N + 1 1 )
CDSCLK2
tA AD CCLK
D CLK
tC
2ADF
tA
DFC2
tA
DH
tA
DL
tO
D
O u tp u t D a ta D7~D0
P ix e l (N -7 )
P ix e l (N -6 )
P ix e l (N -6 )
P ix e l (N -5 )
P ix e l (N -5 )
P ix e l (N -4 )
P ix e l (N -4 )
P ix e l (N -3 )
P ix e l (N -3 )
P ix e l (N -2 )
P ix e l (N -2 )
P ix e l (N -1 )
P ix e l (N -1 )
P ix e l (N )
P ix e l (N )
P ix e l (N + 1 )
P ix e l (N + 1 )
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
1-Channel SHA Mode Timing
Rev. 1.30
7
June 29, 2004
HT82V36
Application Circuits
The recommended circuit configuration for 1-channel CDS mode operation is shown below. The recommended input coupling capacitor value is 0.1mF (see circuit operation section for more details). A single ground plane is recommended for the HT82V36. A separate power supply may be used for DRVDD, the digital driver supply, but this supply pin should still be decoupled to the same ground plane as the rest of the HT82V36. The loading of the digital outputs should be minimized, either by using short traces to the digital ASIC, or by using external digital buffers. All 0.1mF decoupling capacitors should be located as close as possible to the HT82V36 pins.
V 1 2 3 .3 V 4 5 6 7 8 9 10 11 12 13 14 3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0 .1 m F 1 0 m F 0 .1 m F 3 .3 V 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F In p u t 0 .1 m F 1 .0 m F
DD
CDSCLK1 CDSCLK2 AD CCLK OE DRVDD DRVSS D 7 (M S B ) D6 D5 D4 D3 D2 D1 D 0 (L S B )
AVDD AVSS NC OFFSET V IN G CML NC REFT REFB AVSS AVDD SLO AD SC LK SDATA
0 .1 m F
H T 8 2 V 3 6 (C D S M o d e )
V 1 2 3 .3 V 4 5 6 7 8 9 10 11 12 13 14 3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0 .1 m F 1 0 m F 0 .1 m F 3 .3 V 0 .1 m F 0 .1 m F 0 .1 m F DC Level In p u t
DD
CDSCLK1 CDSCLK2 AD CCLK OE DRVDD DRVSS D 7 (M S B ) D6 D5 D4 D3 D2 D1 D 0 (L S B )
AVDD AVSS NC OFFSET V IN G CML NC REFT REFB AVSS AVDD SLO AD SC LK SDATA
0 .1 m F
H T 8 2 V 3 6 (S H A M o d e )
Note: For the SHA Mode, all of the above considerations also apply, except that the analog input signal is directly connected to the HT82V36 without using a coupling capacitor. The OFFSET pin should be grounded if the input to the HT82V36 is to be referenced to ground, or a dc offset voltage should be applied to the OFFSET pin in situation where a coarse offset needs to be removed from the input.
Rev. 1.30
8
June 29, 2004
HT82V36
Package Information
28-pin SSOP (209mil) Outline Dimensions
28 A
15 B
1 C C'
14
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 291 196 9 396 65 3/4 4 26 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25.59 3/4 3/4 3/4 3/4 Max. 323 220 15 407 73 3/4 10 34 8 8
Rev. 1.30
9
June 29, 2004
HT82V36
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2004 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.30
10
June 29, 2004

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